The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that does not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Dual-line first-in-first-out (FIFO) memory elements are commonly used for data synchronizing purposes in large electronic devices, e.g., in switching devices. For example, when data is transferred via a wired coupling for a long distance in large scale switching dies, the data transfer is usually done using dual-line FIFOs that are interspersed along the coupling. For another example, data buffers insides an Internet Protocol (IP) based device usually include a number of FIFOs. The data width of FIFOs can range from a few bits to thousands of bits. Thus, there are usually a large number of dual-line FIFOs spread out all over a system-on-a-chip (SOC) circuit. These FIFOs typically consume a significant amount of circuit area, power and routing resources. Specifically, a conventional dual-line FIFO includes two flip-flops to write the dual-line data bits, and a multiplexer to output data from the two flip-flops. As each multiplexer consumes a significant circuit area, when there are a large number of FIFOs on the SOC, the collection of FIFOs necessitates the use of considerable circuit resources.